The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low powerSchottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDECstandard no. 7A.The 74HC75 has four bistable latches. The two latches are simultaneously controlled byone of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the dataenters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs(nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up timeprior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latchedoutputs remain stable as long as the LEnn is LOW.
