The 74HC/HCT74 is a high-speed Si-gate CMOS deviceand is pin compatible with low power Schottky TTL(LSTTL). They are specified in compliance with JEDECstandard no. 7A.The 74HC/HCT74 are dual positive-edge triggered, D-typeflip-flops with individual data (D) inputs, clock (CP) inputs,set (SD) and reset (RD) inputs; also complementaryQ and Q outputs.The set and reset are asynchronous active LOW inputsand operate independently of the clock input. Informationon the data input is transferred to the Q output on theLOW-to-HIGH transition of the clock pulse. The D inputsmust be stable one set-up time prior to the LOW-to-HIGHclock transition for predictable operation.Schmitt-trigger action in the clock input makes the circuithighly tolerant to slower clock rise and fall times.
